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Help required regarding CADENCE virtuoso

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View attachment ckt.bmp We are attempting to implement a 6-bit Flash ADC in 90nm CMOS technology using CADENCE. We require a 4-bit and 16-bit analog multiplexer (switch) but do not know the internal architecture of the same. Can someone please provide us with some help regarding the schematic of these components.
 
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If someone has done the same or similar projects please do help us. We are facing a fast closing in deadline.
 

You can find good schematics in older databooks from Harris
Semiconductor, Intersil (back when the two were distinct),
Data General, even RCA CD4000 logic. You need a demux
and a rack of switches. But then come the niceties like
break-before-make (so as not to cross-contaminate sample
voltages), charge injection (ditto), tradeoffs in on resistance
vs capacitance, vs leakage, vs settling time and so on.

A very fast ADC with surplus headroom may get by with a
simpler mux than a general purpose piece-part that has
to have good on-resistance linearity across the common
mode range (like, NMOS-only switches with maybe a
charge injection compensation).
 
dick_freebird said:
You can find good schematics in older databooks from Harris
Semiconductor, Intersil (back when the two were distinct),
Data General, even RCA CD4000 logic. You need a demux
and a rack of switches. But then come the niceties like
break-before-make (so as not to cross-contaminate sample
voltages), charge injection (ditto), tradeoffs in on resistance
vs capacitance, vs leakage, vs settling time and so on.

A very fast ADC with surplus headroom may get by with a
simpler mux than a general purpose piece-part that has
to have good on-resistance linearity across the common
mode range (like, NMOS-only switches with maybe a
charge injection compensation).
Click to expand...

Hey thanks a lot...
 

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