shaiko
Advanced Member level 5
Most (if not all) FPGAs/CPLDs have only synchronous D flop flops.
So...How are transparent latches implemeted ?
Is it done by some kind of manipulation on the D flip flop ? If so, what ?
So...How are transparent latches implemeted ?
Is it done by some kind of manipulation on the D flip flop ? If so, what ?