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problem with FSM in verilog

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asraf

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hi there..i post here verilog code for FSM. i could not make the state machine transit from one state to another state. i ran this on simulation platform.please help me








\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
`timescale 1ns / 1ps


module fopen();

reg clk;

/* Declare a array 4 word deep 20 locations wide for 20/4 = 5 hexadecimal words */

reg [4:0] count;
reg [2:0] count2;
reg [0:0] data [0:15]; // we have to control the depth oh data..exp..20 data? 30 data? no of data
reg [3:0] datdis ;
reg [0:3] datdis4 ;
reg state;


reg [2:0] index;

initial
begin
clk<=1'b0;
count<=5'd0;
count2<=3'd0;
index<=3'd0;
end



initial
begin
$readmemb("QPSK_file.txt", data);
end

always
begin
#1 clk<= 1'b1;
#1 clk <=1'b0;
end


///////////////////////////////////////////////////////



always@(posedge clk)
begin
if(count==5'd16)
count=5'd0;
else
count<=count+1'b1;
end



always@(posedge clk)
begin
if(index==3'd4)
index=3'd0;
else
index<=index+1'b1;
end




//////////////////////////////////////////////////////

always@(posedge clk)
begin
count<=count+1'b1;
datdis=data[count];
$display("%d:%d",count,data[count]);
end

////////////////////////////////////////////////////////


always@(posedge clk or count or index)
begin

case(state)

0:
begin
index<=index+1'b1;
count<=count+1'b1;
datdis4[count]<=data[count];
if(index==3'd4)
state<=1;
else
state<=0;
end

1:
begin
index<=3'd0;
state<=0;
end


endcase
end




endmodule
 

Hi asraf,

I have some experience coding state machines in VHDL.
You appear to have multiple concurrent processes setting the count and index registers.
This may create conflict as to what actually happens to the registers.
It would be helpful if I knew what you are trying to achieve.
I found this software useful in the past:
Qfsm | Free Development software downloads at SourceForge.net

Regards,
scanman
 

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