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Error while reading verilog file [Encounter 10.11]

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nisshith

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Hi

I am trying to import an Gate level design in Encounter but while reading the file it shows following error

**ERROR: (ENCVL-319): vinst (buf_dummy__859) for pcell (iu3_nwin8_isets4_dsets2_fpu0_v850_cp0_mac0_dsu1_nwp2_pclow2_notag0_index0_lddel1_irfwt0_disas1_tbuf1_pwd2_svt0_rstaddr0_smp3_fabtech29_clk2x0_1) cell (0) has 0 VTerms.



also it shows the waring

**WARN: (ENCVL-324): Module SNPS_CLOCK_GATE_HIGH_iu3_nwin8_isets4_dsets2_fpu0_v850_cp0_mac0_dsu1_nwp2_pclow2_notag0_index0_lddel1_irfwt0_disas1_tbuf1_pwd2_svt0_rstaddr0_smp3_fabtech29_clk2x0_36 in ../verilog/mp.v will overwrite the previous definition in the same file.


but i checked there only one definition for that module in netlist.

Can somebody please help
 

do you have read a ldb (or liberty) and LEF of this pcell component?
the warning occurs the first you read mp.v, or the second time, and the tools had just indicate he removed from his memory the previous one?
 

No i do not have LEF for this component actually this module calls another module in its definition which is CGLPPRX2_HVT and it is present in LEF.

I am reading mp.v only one time and even if it was read two times the this warning should occur for all modules but it is only occurring for some of them. This is not the main issue main is the Error beacause of which i am unable to import the design in Encounter
 

where come from this netlist? from a synthesis tool, do you run some lint or lec tool on it?
 

i got the netlist from synthesis tool. I have imported same netlist in ICC its working fine there. I can't understand problem here.
 

nisshith,

I am not sure how the milkyway is organised, But my experience with cadence says, If u have the lef views and see if it bussed or bit blasted, Sometime it so happens that netlist used bussed and lef is of bit blasted, and Tool with pop out the warning to those instances/modules. and cadence is very particular with the models used after 10 version. Earlier this error was not reported.

And if my understnding of the above is of, ur calling in the module which has internel to other module, Then include them in ur all/top.lef makes ur work easier.

Try them and let me know if u come up with the similar warnings.
 

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