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efficent alu design with pipelining

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anbuonlymevlsi

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i am doing me-vlsi second semester.next semester i will do project.i am very much interest to design 4 bit alu with efficiently. how we can introduced pipeline here.pls give me any idea.
 

introduction for pipeline depends on what type of operation does your ALU performs. I don't think that there much scope for pipe lining in 4 bit ALU. for every function you perform the output will be generated in one clock cycle only. Like logical and arith. shift you cannot divide these things in two stages, think of something bigger then we can try introducing pipelining. You can try reading basic 5 stage pipeline processor to get more idea about pipelining
 

Hi anbuonlymevlsi,

As nisshith said, for a 4 bit ALU there is no need of any pipeline mechanism. Here is an example where we can insert a pipeline mechanisms. Have you heard about the ARM's AMBA AHB protocol, in that protocol there is a pipeline mechanism. There is a shared Address bus for read and write operation. So if we are performing a burst read/write then it will more cycles to finish after the address had latched, so once the address latched then we can insert the next address before completing the current read/write operation. Means the insertion of next address in the address bus before completing the current task for that we can insert a pipeline mechanism..
 

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