Is there a way to connect multiple drivers to one signal in FPGA Synthesis?

Hi everyone,

Is there a way to connect multiple drivers to a single port in FPGA synthesis. Here is a sample code:

...

signal out: std_logic_vector (7 downto 0);

signal in1: std_logic_vector (7 downto 0);
signal in2: std_logic_vector (7 downto 0);
signal in3: std_logic_vector (7 downto 0);

out <= in1;
out <= in2;
out <= in3;

...

I believe that it is not synthesizable until and unless I use either tristate-buffers or MUX to connect multiple inputs to an output. However, I intend to use the concept of power-gating and I am sure that there will be only one input present for any given instance of time, the others will be powered-off! So, we don't necessarily need a MUX in that case. The question is how could we make the synthesizer realize this fact?

Is there a hack-around to do this without MUX?

regards,
Adeel Pasha

PS: I am Xilinx (ISE) for synthesis...

You cannot do this in an FPGA.
You will have to use a mux.

Lean back and think about what you're doing!

How can the FPGA input know about the said "power gating" of externally connected devices? A digital input is required to interpret the signal as either '0' or '1'. There's no thing like 'unpowered signal'.

In practice, you have two options:

- Connect all drivers to one input port, in other words do the gating externally. You need to know if it can work at all.

- Rely on a known state of the unpowered logic outputs, possibly by adding pull-down resistors. In this case,
will work.