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Throttle decoder circuit

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sahajagarwal

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i/p-pwm throttle control. TTl level PWM throttle control wita base frequency of 2khz and a duty cycle rangining between 10%-90%. 10% full reverse. 90% is full speed. 50%is stop.
o/p-decoded throttle control. A two-bit TTl logic signal, one bit indicating direction(0/1), other bit a PWM TTL signal(0-100%).
please help
 
Last edited:

Analog solution:

A phase detector with a 50% PWM reference signal, low pass filter plus VCO without feedback,
and a VDD/2 comparator for the filter output signal to get the direction signal.
Some positive comparator feedback to achieve a reasonable stop band.
 

erikl said:
Analog solution:

A phase detector with a 50% PWM reference signal, low pass filter plus VCO without feedback,
and a VDD/2 comparator for the filter output signal to get the direction signal.
Some positive comparator feedback to achieve a reasonable stop band.
Click to expand...
Can you please further elaborate it?
 

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