[SOLVED] defining integer type

How can i define and use an integer type containing for example 1,3,5,7 ?

Define where?????

masoud.malekzadeh said:

How can i define and use an integer type containing for example 1,3,5,7 ?

Click to expand...

You can't, integer ranges must be consecutive integers.

KJ

IEEE suggests
An integer is a general-pupose variable used for manipulating quantities that are not regarded as hardware registers.

You can easily in ur design as well as in testbench
integer i; //integer variable min 32 bit size
one thing by declaring integer u donot mean actual register on hardware.

vickyuet said:

one thing by declaring integer u donot mean actual register on hardware.

Click to expand...

Well, in that case, if I declare as

signal i : integer range 0 to 7;

process(clk)
begin
if rising_edge(clk) then
i <= i+1;
If(i = 6) then
A <= 3;
B <= 0;
elsif(i=7) then
A <= 1;
B <= 7;
end if;

end process;

In the above case, the integer is being used as both Storage(A,B) and hardware register(i). Then how can it be just a manipulating quantity
Here integer means nothing more than std_logic_vectors without sign.
Correct me if wrong... :roll:

xtcx said:

Here integer means nothing more than std_logic_vectors without sign.
Correct me if wrong... :roll:

Click to expand...

Nope
integers are integers. slvs are slvs (and they are not even numbers).

The synthesis tool will convert the integer into a 3 bit bus yes, but its not a std_logic_vector (each std_logic has 9 states, the compiled will have 2).

I dont get it.....
Integers when synthesized will be converted to binary numbers for eg, if integer value = 3 then it is similar to std_logic_vector(1 downto 0)....isn't it?.

I presume these two are same
signal a : integer range 0 to 7;
signal b : std_logic_vector(2 downto 0);
signal c : std_logic_vector(7 downto 0);


Because assigning
a <= 7
b <= "111"
c <= "00000111";
are all same. Even I think C doesn't take more than 3-bits if used wisely

you have to think about the synthesised world when writing VHDL, but they are two separate worlds. VHDL is a stongly type language, logic is a load of logic.

In VHDL land - an integer is a non binary type. but it translates to a binary type in logic world.
A std_logic_vector in VHDL is NOT an integer, and should NOT be treated as an integer. If you want a binary number - use the signed or unsigned type (thats what they're there for). But remember std_logic values can be 'U' or 'X' or the other non-translatable values. These are v useful for simulation, but useless on real hardware (because they dont exist).

So yes, at the end of the day, A and B will translate to the same thing on an FPGA (C might, if bits 3 to 7 remain constant).

TrickyDicky said:

A std_logic_vector in VHDL is NOT an integer, and should NOT be treated as an integer. If you want a binary number - use the signed or unsigned type (thats what they're there for).

Click to expand...

I agree that slv is NOT an integer, but integer can only be a slv. Mmm...could also be signed\unsigned too. What happenes when you write

a <= 3;

This will be translated into "11" if declared with range keyword. Integers will ALWAYS synthesize into std_logic_vectors, whats wrong in using so?. But the reverse is not right as you said. I usually find it easy to use integer instead of binary slv for things like counter\timers, etc

stop talking about std_logic_vectors - in the FPGA they get converted to logic, which has nothing to do with std_logic_vectors. What it gets converted to will depend on the target device.