Technology is Shrinking - Is it near to freeze ?

As we see in VLSI field, our technology has already reached 28nm, 18nm and so on.

With gate_size, range keep on decreasing, i believe one or the other day, it will freeze for sure.

Do researchers, targetting on pico level, pm technology like that (pico meter 10^-12)?

Is MEMS, goona do anything revolutionary here.,

please share your comments >>>>>

Hariharan B

Currently, the industry is moving more and more towards parallel processing to compensate for the limits of Moores Law.
The research in the sub-nano field hasn't matured. I don't think it'll freeze - "evolution" is the key word.

I too wonder whats gonna be last trigger to this nm technology . Length can't be reduced to zero , we have already come to 19 nm/22nm , upto when can we reduce length. Don't know whether this is wrong or what , but i read that 2015 will b bottleneck for moores law. Nanotechnology can light up this field.

Somebody will invent something Don't Worry Dude.

hariharan.gb said:

As we see in VLSI field, our technology has already reached 28nm, 18nm and so on.

With gate_size, range keep on decreasing, i believe one or the other day, it will freeze for sure.

Do researchers, targetting on pico level, pm technology like that (pico meter 10^-12)?

Is MEMS, goona do anything revolutionary here.,

please share your comments >>>>>

Hariharan B

Click to expand...

Nope my friend, only thing what can freeze are ours wallets.

the statement is debated though moore's law is there and all in the last 18 months the no of trannies have not been doubled in an ic chip if i am not wrong so the fact i would love to put is that the day will come in the near future that the size may be infinitesimally smaller but the capacity may have been multiplied a googol times

Intel details 10nm, 7nm, 5nm process roadmap
https://www.bit-tech.net/news/hardware/2012/05/14/intel-process-roadmap/1

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Semiconductor giant Intel has revealed its roadmap for process technologies, which will see 10nm, 7nm and 5nm released beginning in 2015.

The majority of the industry is working on a 22nm process at present, including Intel's recently-launched Ivy Bridge processors. The next step for the semiconductor industry is 14nm, which Intel is planning to introduce with its Broadwell processors - the successor to the new microarchitecture Haswell parts, based on the same 22nm process as Ivy Bridge as part of Intel's 'tick-tock' development cycle.

Ivy Bridge will make its entry through the LGA1155 platform in 2012, it will make up the 2012 Core processor family. Haswell is the next-generation architecture that succeeds Sandy Bridge and IvyBridge, it will be built on the 22 nm process, and is expected to arrive in 2013. Roswell is its optical shrink to 14 nm, slated for 2014. Looking deep into the decade, there's Skylake architecture, that will span across 14 nm and 10 nm processes with Skymont. This model ensures that Intel has to upgrade its fabs every 2 or so years, an entirely new micro-architecture every 2 or so years as well, while providing optical shrinks every alternating year. Optical shrinks introduce new features, increased caches, and allow higher clock speeds. 10 nm for processors by 2018 sounds realistic looking at the advancement of NAND flash technologies that are pushing the boundaries of fab process development. NAND flash is much less complex than processor development, and hence serve as good precursors to a new process.



Like I say earlier only thing what will freeze are ours pockets and wallets in it.

:wink:

Thanks for the replies, guys :wink:
- but when we think beyond the estimate graphs, (say for example - the very famous question - "what would be next"), i hope we still not got a clue to predict further!

- Hey <tpetar> - thanks for the graph:
- But do we have something to think beyond CMOS, a complete new revolution of a "X" cell, which can replace CMOS to proceed further ?:?:

Hariharan.

lesser prob in replacing cmos completely yer

but most expect they be replaced completely by some thing new

hariharan.gb said:

Thanks for the replies, guys :wink:
- but when we think beyond the estimate graphs, (say for example - the very famous question - "what would be next"), i hope we still not got a clue to predict further!

- Hey <tpetar> - thanks for the graph:
- But do we have something to think beyond CMOS, a complete new revolution of a "X" cell, which can replace CMOS to proceed further ?:?:

Hariharan.

Click to expand...

Next is pm (pico metre).

tpetar said:

Next is pm (pico metre).

Click to expand...

pm is like operating within a single atom right is it possible

even harder to imagine

We cant see behind corner, in best case today with ours science we can see just in front.

Can imagine that we are in 80-90th say '87-'90 and someone tell you about 5nm processors.:grin:

yeah true
similarity can be seen those days are today's view on pm tech

squids and josephson's devices are swell super conductor tect can sprout if newer innovations are found in the field of higher temperature super conductors

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check this link out it is quite amazing

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I do agree with you rodgerwxh

TECHNOLOGY SCALING HAS CHANGED BUT DOES NOT SEEM TO BE ENDING, at least not yet.

Before I proceed, please keep in mind that all companies, including Intel are not being 'honest' or 'clear' about their transistor technologies. For example, when Intel says '22nm' node or any foundry says '28nm' node, the actual transistor dimensions are not exactly the same. For example, if you check Intel's publications at VLSI Technology 2011, IEDM 2012, you'll realize that their actual gate lengths are in the range of 30~40nm. '22nm' is the NODE name based on the historic tradition of naming channel lengths with 0.7X scaling from the previous generations. 45x0.7=32, 32x0.7=22. However, traditional scaling of channel length is not giving any improvements in transistor performance but is increasing undesirable effects such as leakage currents.

Starting at 90nm, traditional scaling stopped (scaling in transistor length) or at least slowed down. The increase in performance was achieved from channel strain engineering, using High-K metal gates at 45nm node to reduce gate leakage and other techniques. Intel realized that scaling beyond 32nm was becoming too difficult and decided to move to 3D channel transistors called FinFETs (in order to differentiate from actual finfets invented at UC Berkeley in 1999-2001, they call it Tri-gate). 22nm node was implemented using tri-gate transistors and the rest of the foundries are following up with FinFETs at the 14nm node. Again, 14nm is not truly 14nm gate length, but something larger. But you'd get a performance improvement 'as if' you were moving to a scaled node. Also please note that metal pitches and poly pitches were being scaled to give reduced area. But the actual transistor channel length which most of us talk about, has not scaled at the same pace.

The foundries have already announced 10nm technology node. Intel is supposedly working on III-V material based quantum-well tri-gate transistors for probably the 10-7nm nodes. The next in line is silicon nanowires and/or nanotubes. Transistors with dimensions in the 4nm range have been demonstrated, but real design using them is a pain-in-the-butt. Scaling of technology nodes is not necessarily done using just technology innovation, but 'economics' is a huge motivation. Historically, moving from one node to the another, area of the chip reduced, the number of transistors you could put in a given die increased, performance improved, power reduced. Hence, it was 'economical' to move to the next node because you could sell more chips at the same price than you could at the earlier node. Also power/performance improved. This is what Moore's Law really is, reducing the price of the transistor (unlike, just scaling which Intel uses for marketing). Check Gordon Moore's original paper for more information. From that point of view, Moore's Law is nearly dying, because putting these transistors at 20/22nm node is not getting cheaper. Lithography constraints are a huge topic and are actively under research. Current generation lithography uses 193 nm light to print features which are in the range of 64-90nm (not channel length, but metal pitches and transistor poly pitches which truly determine scaling).

Numerous 'exotic' technologies are discussed by tech websites and are mentioned in journals like 'Nature'. However, the actual implementation will be determined based on just two factors: Performance and Cost. If the cost is too high, none of these new technologies will be used by the industry because no one would like to buy at $2000 iphone just because it gives you 20% higher performance using carbon nanotubes. Additionally for most of these technologies, reliability is a huge concern. The tech industry understands silicon and manufacturing with it, so they are going to push it as far as they can. But yes, technology scaling is at an interesting inflection point, where newer exotic materials/methods may find its way into manufacturing. Traditional Moore's Law is nearing its death, traditional scaling has slowed down, but it definitely is not going to end...not at least in the near future (5-10 years), is my guess, based on the most recent research in this field.

For now to solder one more 8-bit microcontroller to board, it looks like as good idea. :smile:

If older tech system is used on good way and have good purpose its better then advanced tech system which is used on wrong way, or is not used with full capabilities.

tpetar said:

We cant see behind corner, in best case today with ours science we can see just in front.

Can imagine that we are in 80-90th say '87-'90 and someone tell you about 5nm processors.:grin:

Click to expand...

But with hell lot of congestion issue in Physical design, and in many seminars I heard the same thing, that we cant think beyond 5 or 4 nm.
FinFET's or other way of workaround, we are trying with nm., not with pico.,
If any pico research kind of info you have, can you share please.

Hariharan B