allanvv
Advanced Member level 4
Ring oscillator VCO design
I'm designing a ring oscillator VCO which can be low performance, since I won't care much about phase noise or great frequency stability. However, I will need a very wide tuning range of something like 1 MHz to 2 GHz with minimum amount of control signals (so simplicity is desired). Also, I don't have much concern about power usage.
When I see papers with ring oscillator test structures for instance, they use a large amount of stages, like 31. Why is this? Just to get a lower frequency?
Are the inverters typically minimum size? Is there any benefit in using bigger inverters, such as better reliability in case of process variations? Even a 31-stage oscillator in my process will be extremely fast. Should I use longer length transistors to slow it down or add more stages?
Any quick recommendations about the design in general for wide tuning range? I'm planning on using current starving, and bringing out an analog voltage to tune with. If this can't get the oscillation frequency slow enough, I'll also add in a digital control signal to switch in a bunch of capacitors at each inverter, or even just put a divide-by-N circuit in there.
edit: Also, linearity isn't important. This is for generating a clock, so outputs should be logic level.
I'm designing a ring oscillator VCO which can be low performance, since I won't care much about phase noise or great frequency stability. However, I will need a very wide tuning range of something like 1 MHz to 2 GHz with minimum amount of control signals (so simplicity is desired). Also, I don't have much concern about power usage.
When I see papers with ring oscillator test structures for instance, they use a large amount of stages, like 31. Why is this? Just to get a lower frequency?
Are the inverters typically minimum size? Is there any benefit in using bigger inverters, such as better reliability in case of process variations? Even a 31-stage oscillator in my process will be extremely fast. Should I use longer length transistors to slow it down or add more stages?
Any quick recommendations about the design in general for wide tuning range? I'm planning on using current starving, and bringing out an analog voltage to tune with. If this can't get the oscillation frequency slow enough, I'll also add in a digital control signal to switch in a bunch of capacitors at each inverter, or even just put a divide-by-N circuit in there.
edit: Also, linearity isn't important. This is for generating a clock, so outputs should be logic level.
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