negative integer to std_logic_vector converter

Hi every one

I want to convert negative integer number to std_logic_vector in xilinx fpga. I want to convert it in 16 bit.
is it correct :
vout <= conv_std_logic_vector(-32000,16);

is it converting to std_logic_vector in 2`complement?
Regards
Arasg

I don't know the details of the "conv_" functions, since I don't use them.
If you are learning VHDL now, I recommend that you forget the std_logic_arith, std_logic_unsigned and std_logic_signed libraries.
numeric_std replaces them all, and that happened 20 years ago!
If your VHDL book uses the "conv_" functions, throw it away and get another book.

With numeric_std you do it like this:

vout <= std_logic_vector(to_signed(-32000,16));

If you do arithmetic operations on "vout", you can probably save some trouble by having it as type "signed":

signal vout: signed(15 downto 0):
........
vout <= to_signed(-32000,16);

and how can i convert std_logic_vector to integer in this library you said?
one more question : Why do you say std_logic_arith, std_logic_unsigned and std_logic_signed libraries are not good? Can you prove it to me?

---------- Post added at 07:51 ---------- Previous post was at 07:09 ----------

beside it didn`t wotk, I will put my code here which is voltage limiter and I will show you the error. I am using ISE design suite

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all ;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Limitter is
Port ( CLK : in STD_LOGIC;
vin : in STD_LOGIC_VECTOR (15 downto 0);
vout : out STD_LOGIC_VECTOR (15 downto 0));
end Limitter;

architecture Behavioral of Limitter is

begin


process(CLK) --process with sensitivity list.

variable buff_IN : signed(15 downto 0);

begin --"begin" statment for the process.


if rising_edge(CLK) then

buff_IN := (to_signed(vin,16));
if buff_IN > 32000 then
vout <= std_logic_vector(to_unsigned(32000,16));
elsif buff_IN < -32000 then
vout <= std_logic_vector(to_signed(-32000,16));
else
vout <= vin ;
end if;


end if;

end process;
end Behavioral;

and the error is :
ERROR:HDLParsers:808 - "D:/Xilinx works/FILTER_LPF/DAC_TEST/Limitter.vhd" Line 54. to_signed can not have such operands in this context.

arash rezaee said:

and how can i convert std_logic_vector to integer in this library you said?

Click to expand...

buff_in <= signed(vin);

one more question : Why do you say std_logic_arith, std_logic_unsigned and std_logic_signed libraries are not good? Can you prove it to me?

Click to expand...

They are not part of the VHDL standard. They were written by synopsys in 1992, and have not been updated since. Numeric_std was released with the VHDL 93 standard, and is part of standard VHDL.
Unfortunately, most books people read were written in the early 90s, or some designers still think its the early 90s, and teach new people like that.

ok. thanks. can you help me with the code I wrote here? is it correct that I control the voltage like this?

I have no idea without the DAC datasheet.

arash rezaee said:

Why do you say std_logic_arith, std_logic_unsigned and std_logic_signed libraries are not good? Can you prove it to me?

Click to expand...

With those libraries, it is very difficult to use both unsigned and signed in the same entity.

I attach a very good document about the casts and conversions between std_logic_vector, signed, unsigned and integer in numeric_std.