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VHDL and VERILOG how i can connect together

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How i can integrate a verilog code into an VHDL code?
I have a code in verilog and i want to use it together with a vhdl code how can i do it ?
 

Re: VHDL and VERILOG hoa i can connect together

First of all, you need a simulator with a mixed mode licence (Minimum modelsim PE)

second, create a component in the VHDL architecture that matches the port description of the verilog module, and make all ports std_logic.
Instantiate it and it should just run fine.
 

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Re: VHDL and VERILOG hoa i can connect together

anyone has know the X-HDL converter of X-Tek corporation?
 

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