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Carry Look ahead adder

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abhiverma812

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Hello experts,

I am making a full custom design of a carry look ahead adder as my lab assignment. For that I need multiple input NAND gates, varying from 2 input to 5 input (at max). The design constraint is to get minimum delay and minimum area. Please recommend ways to reduce the 2 constraints.

Thanks in advance.
Abhishek
 

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