i have selected the scan style as -clocked scan in DFT compiler, instead of mux based design
my flip-flop module is as below,
module FF(clk1,clk2,si,data,q)
wire clk;
clk=clk1|clk2;
always@(negedge clk)
begin
if(clk1)q=si;
if(clk2)q=data;
end
endmodule.

The above code fails in the compile -scan with the error "No SCAN equivalent Found";

Further i don how to define the clock periods for clk1 and clk2;there are warnings like "clk1 cannot capture while clk2 is off".

Please give the flow in DFT compiler for the clocked_scan style and LSSD scan style.
Please do reply at the earliest