Colin Chong
Newbie level 1
Hi there, I am currently work on the VLSI design and I come across a little problem here on the SR flip flop.
Here is the SR flip flop logic circuit:
Here is the Digital wave form:
I need to know how should I construct a timing diagram for this flip flop. The timing diagram should consists of 'Stable' and 'Changing' stage for the S and R input and the Q output. Thanks :smile:.
Here is the SR flip flop logic circuit:
Here is the Digital wave form:
I need to know how should I construct a timing diagram for this flip flop. The timing diagram should consists of 'Stable' and 'Changing' stage for the S and R input and the Q output. Thanks :smile:.
