Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Regarding setup and hold violaitons

Status
Not open for further replies.
P

pavan.mk

Newbie level 6
Joined
Nov 28, 2011
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Bangalore
Activity points
1,375
Regarding setup and hold violations

1) Can anyone tell me equation wise how we calculate setup and hold slack? (including uncertainity and skew)
2) How do we fix setup and hold violations?
3) Why hold analysis is done after clock tree synthesis?
4) How setup check can be done even before clock tree synthesis?
 

Setup time equation:
Tcq + Tcomb < Tskew +T - Tsetup

Hold time equation:
Tcq + Tcomb >Tskew + Thold

Setup violation depends on the data path delay while hold violation depends on the clock path delay. Before CTS clock path is taken as ideal. We don't have skew and transition numbers of the clock path. Clock is propagated after CTS that why hold violations are fixed only after CTS.

https://www.edaboard.com/threads/232411/#2
 

Thank you sir.
In the SDC file, we provide set_input_delay and set_output_delay. Why do we use that? And how would we be able to fix those values?
 

Input delay and output delays are defined at input and output ports of the blocks that are part of a top level design. set_output_delay is defined for output port. Output port of a block will be connected to a input port of other block. So that reg2out of your block and in2reg of other block becomes a complete reg2reg path. You have to meet this path in one clock cycle. set_output_delay accounts for time that is required to meet in2reg path in other block so this time is subtracted from clock period and you have to meet your reg2out in the remaining time so that total reg2reg path can be meet. Same thing is applicable to set_input_delay.
 
Ok, thank you sir.
Regarding congestion, we say that whenever the required number of tracks is less than the available number of tracks then it leads to congestion.
How do we get know the required and available routing tracks?
 

Tool does a trial route to get number of requires tracks. Available number of tracks in a metal layer are fixed.
 

yadavvlsi said:
Tool does a trial route to get number of requires tracks. Available number of tracks in a metal layer are fixed.
Click to expand...

Hello Sir,

can you explain this in detail?

Thanx you.
 

ramesh28 said:
Hello Sir,

can you explain this in detail?

Thanx you.
Click to expand...

During pre-route (post place or post cts), your tool will perfom virtual routing and routing congestion analysis. Here the number or routes passing on each tracks are analyzed will be feed back to you by the routing/congestion analyzer tool.
From there on you would know the routing distribution and address areas where routing congestion will be a problem.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top