how to reduce spikes of the voltage doubler

In the design the voltage doubler is used to power internal circuits.Two CAP are external.
simulation show big spikes on Vout when wire induction is took in account, especially at the transition from transfer phase to charge phase, a big minus spike occur.
Do the switching sequence or the rising speed of the switch driving signal have effect?
Could anybody give me some help ?

I assume this is a switching design.

Does it feed AC square waves to the capacitors? Or does it feed DC pulses?

With AC square waves, a spike happens when you reverse the polarity on a charged cap. Immediately its charge adds to the new applied voltage. This doesn't happen with DC pulses. Nor does it happen with AC sine waves.

The elevated voltage quickly drops as the capacitor responds. Thus its appearance of a spike.

BradtheRad, Thanks a lot!
But I have no idea of "feed AC square waves"or "feed DC pulses".
As a matter of fact,the switch driving signal is as follows:

the input is a dc voltage say 3V and the output voltage is 5.5V,switching freq. is controlled by the output voltage and the circuit is omitted here.
in the design the output Voltage is used for the input of a regulator,the load is assumed constant.
In my simulation, 6nF bonding wire inductance and 200m Ohm resistance is added in sires to the two external cap.The output spikes happen at the inner side of the inductance beside Cout.

6nH is a mighty long bond wire. You might check that for
realism. It could be reasonable with a real lousy large pkg.

You probably wouldn't lose much by shrinking the FET sizes
as long as the energy is fully transferred within the clock
phase. Call it maybe 3 tau and done, your FET Ron can be
figured for a given clock and cap value. A more leisurely
edge will tax the inductance less and make a quieter pump.

Your waveform sketch looks like some of the switch phases
are not very non-overlap. You might want to focus on the
FET terminal currents looking for any instances of cross-
conduction, make sure that your clock-field is entirely
proper.

Thanks! Dick_freebird,

6nH is indeed a bit large magnitude for double bonding wire in a sop-28 pkg,i will check

Do you mean i can reduce the width of the switch FET to tax the inductance less? Or maybe the switch can be driven more gently? Could you give detailed theoretical explanation or give me some references? Thanks!

As for the switching phase, for sw1 sw3 sw4 are PMOS, during charging phase sw2 and sw3 closed and sw1 and sw4 are open; during transfer phase sw1 and sw4 are closed and sw2 and sw3 are open; two phases are non-overlap, so I guess such cross-conduction does not exist.

But in each phase, does some better switching sequence exist? I tried switching sw4 off before sw1,it seemed that the minus spikes is smaller and I took it as a consequence of different LC value when I switch sw4 off. Am i right or wrong

By the way,what did you exactly mean by "the
FET terminal currents" ?I am not familiar.It seems that i should look for some references first.
Thanks!