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Issue with .lib files

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satishgra

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Hi,

I have generated liberty files for complex IP's. Unfortunately, some of the arcs have non-monotonic delay values. How can I overcome this as re-running the simulation is not really helping.

How will this impact the backend team who use this .libs for completing static timing analysis.

Regards,
Satish Grandhi
 

time the arc and check the standard cell .lib for each instance in path.the non-monotonous delay would be coming from one of these.
 

I am assuming delay numbers are monotonic because they have to be monotonically increasing. If that is not the case then you will have see your circuit as there is something wrong there. I think the non-monotonocity will be there for setup/hold arcs. You can pad the numbers a little bit to make it monotonic in nature. non-monotonicity will cause library compiler to give errors/warnings. Also the timing will get impacted at the chip level. You have to check you setup for sure as this might be a real problem.
satishgra said:
Hi,

I have generated liberty files for complex IP's. Unfortunately, some of the arcs have non-monotonic delay values. How can I overcome this as re-running the simulation is not really helping.

How will this impact the backend team who use this .libs for completing static timing analysis.

Regards,
Satish Grandhi
Click to expand...
 

Timing sign off is not accurate through such lib pins and can be risky.
I think you should try to analyze why delays are non-monolithic.
 

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