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How to resolve or reduce the bandwidth shrinkage?

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chinboon

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Bandwidth shrinkage

Hi everyone. Need some advice from you all. Basically when we cascade amplifiers we faced the problem of bandwidth shrinkage. Is there any way where i can resolve or at least reduce the bandwidth shrinkage.

From the text books for example Franco and such we can find numerous formulas to have the widest bandwidth however this is not a transistor level approach. What i want is the method to resolve the effect. I notice that by adding a buffer befoire connecting to the next stage of the amplifier the effect would be reduced.

Is the input capacitance of the amplifier a big issue for the shrinkage. Please advice.
 

Re: Bandwidth shrinkage

If you are limited to real axis poles, the best you can do is have a gain of 1.7x per stage and maximize the stage bandwidth. Your suggestion of a source/emitter follower at the output of each stage will reduce the effects of the following stage capacitance.
 

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