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What is the differences between .edf Netlist file and .vhd Netlist file?

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sydundar

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I have a compiled netlist (purchased ) which is a .edf file and seller company said me that you need to use .edf file , dont synhesize leave as a black box But i coulndt do that i think my Libero IDE wants .edn file. After that i used a .vhd file which send us also with the .edf file . I have simulated and used it on a hardwire no problem occured.

I want to learn that what is the difference between .vhd Netlist and .edf netlist ?


Thanks.
 

A VHDL file is source code
and EDF file is a synthesised bit of code, hence why you cannot simulate it. You normally leave the block as a black box and add it in at the fitter stage.
 

Tehere is also .vhd netlist file not only edf file. I want to learn what is the differences. What happned if i used .vhd netlist file instead of .edf which is sended to me both .vhd netlist and .edf netlist.
 

There is no such thing as a VHDL netlist - it will be source code that you should be able to simulate. It could just be a design built using primitive components rather than behavioural code.
 

Yes .vhd netlist is a design built using primitives. Netlist is also built in using primitives? im i wrong?

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I am so confused that what is what :)

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TrickyDicky said:
There is no such thing as a VHDL netlist - it will be source code that you should be able to simulate. It could just be a design built using primitive components rather than behavioural code.
Click to expand...

if it i can simulate it why i also need a netlist file. I can both simulate and run in hardwire???
 

The VHDL netlist will be VHDL code instantiating primitives (so simulatable if you have the simulation libraries for the primitives). THe edf looks more like the netlist output of any schemtic building tool (and not simulatable). The VHDL netlist needs to go through synthesis, but the edf is already synthesised.
 

TrickyDicky said:
The VHDL netlist will be VHDL code instantiating primitives (so simulatable if you have the simulation libraries for the primitives). THe edf looks more like the netlist output of any schemtic building tool (and not simulatable). The VHDL netlist needs to go through synthesis, but the edf is already synthesised.
Click to expand...


Himm , So if i have the simulation libraries for the primitives, vhd netlist is better than edf netlist because i can both simulate and run in hardwire. In this case i dont need edf netlist?

According to me; Maybe one advantages of edif netlist is; it contains manually route informations, if there is no manually information in edf netlist vhd netlist is similar with edf netlist.
 

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