rogeret
Member level 4
behind a downsampling module, synchronize or not
Hi,
I have two clocks: one is clk1 of 30.72M and the other is clk2 of 1.92M(30.72M/16). They are both driven by the same PLL and the phase delay between them is set to 0.
The DataEnable signal is like the following diagram. DataEnable is a clockwide pulse generated by a clock dividor composed of a counter and a comparator in clk1 domain.
Q1 is driven by clk1 and DataEnable. So Q1 changes exactly every 16 periods , which means the throughout rate of Q1 is the same as the frequency of clk2.
My doubt is:
1.with 0 phase delay, clk1 and clk2 are driven by the same PLL and the throughout rate of Q1 is the same as the frequency of clk2, is it necessary to employ a Synchronizer Scheme between Q1 and D2?
2.If it is necessary, how to do it?
Traditional method to synchronize a bus is the handshaking protocol or FIFO. BUT
a. since this module follows a downsampling module which requires this to operate continuously like stream, there is no enough time for handshaking.
b.because of the characteristic of downsampling, I just need to pick the last one of the 16 samples and then overwrite the whole 16 ones every time, which is not compatible with a FIFO.
NOW, my opinion is to employ a RAM with 16 addresses and to write D1 continuously to it in clk1 domain from the 1st address to the 16th address and to read continuously in clk2 domain just from the 16th address. Meanwhile , employ a synchronizer scheme to detect the first Dataenable pulse in clk1 domain after the reset_n deasserts to start reading the RAM in clk2 domain.
Any other suggestion?
Thanks!
Rogeret
Hi,
I have two clocks: one is clk1 of 30.72M and the other is clk2 of 1.92M(30.72M/16). They are both driven by the same PLL and the phase delay between them is set to 0.
The DataEnable signal is like the following diagram. DataEnable is a clockwide pulse generated by a clock dividor composed of a counter and a comparator in clk1 domain.
Q1 is driven by clk1 and DataEnable. So Q1 changes exactly every 16 periods , which means the throughout rate of Q1 is the same as the frequency of clk2.
My doubt is:
1.with 0 phase delay, clk1 and clk2 are driven by the same PLL and the throughout rate of Q1 is the same as the frequency of clk2, is it necessary to employ a Synchronizer Scheme between Q1 and D2?
2.If it is necessary, how to do it?
Traditional method to synchronize a bus is the handshaking protocol or FIFO. BUT
a. since this module follows a downsampling module which requires this to operate continuously like stream, there is no enough time for handshaking.
b.because of the characteristic of downsampling, I just need to pick the last one of the 16 samples and then overwrite the whole 16 ones every time, which is not compatible with a FIFO.
NOW, my opinion is to employ a RAM with 16 addresses and to write D1 continuously to it in clk1 domain from the 1st address to the 16th address and to read continuously in clk2 domain just from the 16th address. Meanwhile , employ a synchronizer scheme to detect the first Dataenable pulse in clk1 domain after the reset_n deasserts to start reading the RAM in clk2 domain.
Any other suggestion?
Thanks!
Rogeret
Last edited:
