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[MOVED]TSMC CMOS 180nm Maximum VDD

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lambchops511

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Hi all,

I am designing for the TSMC 180nm.

What is the maximum VDD I can use?

If I make my transistor width to 250nm, can I increase my VDD? or would I have to use the TSMC 250nm process for that?

Generally, if I use TSMC 180nm, but I create some of my transistors as L=250nm, then I can basically treat it as TSMC 250nm.. correct?

Many Thanks.
 
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lambchops511 said:
Generally, if I use TSMC 180nm, but I create some of my transistors as W=250nm, then I can basically treat it as TSMC 250nm.. correct?
Click to expand...
No, not at all!

1. Not the width W is controlling the electric field strength, but the length L , i.e. you have to increase min. L !
2. The gate oxide thickness tox limits Vgs and Vgb, i.e. you are (possibly) not allowed to use a Vgs=2.5V . Ask the foundry!
 
whoops. i had a typo in the original post . I meant L=250nm not W=250nm.

How would I ask the foundry? Like find a contact email on TSMC website?
 

lambchops511 said:
How would I ask the foundry? Like find a contact email on TSMC website?
Click to expand...
Yes; Vgs(max) should also be found in the PDK docu. And they might offer a 2.5V option for their 180nm process (means: 2 different oxide thicknesses, more masks, 10-20% more expensive).
Also, mosis could possibly give you this info.
 
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thanks for the reply. seems like I need to use 350nm for the 5V vdd.
 

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