jaya sree
Member level 3
hai
in p and r flow , i am seeing many registers's clock pin with no clock ( in the reports from synthesis) . Some of these clock pins are connected to clock gaters ( their input is coming from clock gaters output ) and some of clock pins are connected to tie cells. my doubt is :
1) if clock pins are connected to clock gaters then why these registers are given in no clock list
2) clock pin is connected to tiecell , is this acceptable
---------- Post added at 14:11 ---------- Previous post was at 14:09 ----------
check_timing command showed these registers with no clock
in p and r flow , i am seeing many registers's clock pin with no clock ( in the reports from synthesis) . Some of these clock pins are connected to clock gaters ( their input is coming from clock gaters output ) and some of clock pins are connected to tie cells. my doubt is :
1) if clock pins are connected to clock gaters then why these registers are given in no clock list
2) clock pin is connected to tiecell , is this acceptable
---------- Post added at 14:11 ---------- Previous post was at 14:09 ----------
check_timing command showed these registers with no clock