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thanks for your reply yadav,will u plese consider this query " i took one testcase in 65nm, for that block after adding filler cells i noticed that there is improvement in timing ,at this stage i am not done any change except adding filler cells what will be the reason for improvement in timing?"
thanks for your reply yadav,will u plese consider this query " i took one testcase in 65nm, for that block after adding filler cells i noticed that there is improvement in timing ,at this stage i am not done any change except adding filler cells what will be the reason for improvement in timing?"
Only attribute I can think of in this case is crosstalk. You may have unintentionally added shielding to same of the nets or cells by adding these filler cells
1) a) Due to close proximity of nmos and pmos in a cmos design may lead to formation of two bipolar transistors causing latchup effect. In order to
prevent this undesirable effect, additional guard rings must be built around the nMOS and the pMOS transistors.
b) Supply rings are VDD and VSS supply which provide supply to the power straps providing power to all the cells in the design.
Only attribute I can think of in this case is crosstalk. You may have unintentionally added shielding to same of the nets or cells by adding these filler cells
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