How much of a heat gradient does a 2mA resisitve ladder create?

Hello all,

I am designing a resistive ladder to generate some reference voltages. I am worried about a thermal gradient being created from this resistive ladder in a 90nm TSMC process. I would think 2mA's of DC current isn't much, so should I worry about it producing any significant heat on chip?

Jgk

jgk2004 said:

I would think 2mA's of DC current isn't much, so should I worry about it producing any significant heat on chip?

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I'd think 2mA*1V=2mW produced in a volume of -- say -- 0.5µm*2µm*0.1µm=0.1(µm)³ is quite a lot -- without thermal dissipation it would heat up this silicon volume by about 12 K/ns . You need a 2D or 3D thermal flow solver to calculate its steady state temperature and thermal gradient.

So I'd suggest not to use a poly resistor, because it's totally embedded in ≈0.3 .. 0.5µm thick SiO₂ (or oxy-nitride) which has a rather low thermal conductivity (≈ 1 µW/K*µm). As you only need relative resistance accuracy, I think you'd better use a junction isolated (salicided, of course) n+ resistor in substrate (or p+ in n-well), as silicon's thermal conductivity is larger by a factor of about 150 .

Hi Erikl,
Thanks for the input. Do I have to worry about anything when using N+ diff resistor with salicide? Any downfalls or problems? I have just always used P+ poly.. Do I have to worry about any type of latch-up, What about the voltage dependence on diff resistors? Just wondering but is this included in the simulations?

Jgk

Hi John,

jgk2004 said:

Do I have to worry about anything when using N+ diff resistor with salicide? Any downfalls or problems?

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No, if you just can rely on relative accuracy -- or resistance matching.

jgk2004 said:

I have just always used P+ poly..

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This is ok for low power, or if you need a low voltage dependency (s. below).

jgk2004 said:

Do I have to worry about any type of latch-up

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No, not that I knew. Anyway, I'd spend an extra guard ring. It also keeps active devices afar from the heat source.

jgk2004 said:

What about the voltage dependence on diff resistors?

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This, unfortunately, is a factor of 10 .. 100 worse than the poly's. But if you rely on resistance ratios -- and on well characterized models (s. below) -- this shouldn't matter.

jgk2004 said:

Just wondering but is this included in the simulations?

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Depends on your PDK, of course. Ours have always been characterized quite well, including first & second order TCs & VCs (re. docu + SPICE/SPECTRE models). VC1(N+ diff resistor with salicide) usually is lower than that of P+ .

BTW: ESD input protection resistors (kΩ range) always have been diff. resistors. Why? Because a single HBM 4kV pulse would melt a poly resistor!

Have fun! ;-)
erikl

Erik - voltage dependance will matter since it is a resistive ladder, presumably for a DAC reference. I suppose you could put each res in its own well if possible, but it would probably be just as area efficient to build a wider poly resistor out of low sheet poly.

Where did you get those numbers for heat? Is that really 12 degrees K/nano-second? Roughly, how many ns before it would settle out? I was surprised that it would matter that much.

RobG said:

voltage dependance will matter since it is a resistive ladder, presumably for a DAC reference.

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Right -- if these diff. resistors aren't well characterized re. their voltage dependencies -- I mentioned this necessity above. But if they are -- and you can rely on them like on your MOS models -- there's no reason why you wouldn't find the proper resistor ratio, because the ladder will surely be supplied by a highly constant buffered bandgap reference voltage.

RobG said:

I suppose you could put each res in its own well if possible, but it would probably be just as area efficient to build a wider poly resistor out of low sheet poly.

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I don't think there are several wells necessary: a single N+ ladder chain on substrate is enough, preferably with a guard ring around. But you're right of course with your remark re. the usage of wider poly resistors: then the power can be dissipated through a larger area.

RobG said:

Where did you get those numbers for heat? Is that really 12 degrees K/nano-second? Roughly, how many ns before it would settle out? I was surprised that it would matter that much.

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Remember, this value was given for an unrealistic case of no heat dissipation at all. Starting from a silicon volume of 0.1(µm)³ (s. above), with an Si density ρ=2.33 g/cm³ this equates to a mass m=0.233e-12 g , and with its atomic weight of 28.1 this corresponds to M(Si)=8.3e-15 mol .

With silicon's molar heat capacity MHC≈20 J/(mol*K) (all values from wiki/Silicon), the temperature increase per time ΔT/t = P_el / (M(Si) * MHC) = 2e-3 W / (8.3e-15 mol * 20 Ws/mol*K) = 12e9 K/s = 12 K/ns .

Erik - My gut feel is that is way too much temp increase, but I don't know. Chips are built on SOI and they don't burn up.

I don't know if the volt-co is large enough to cause him problems - probably not. In addition, I think if you take the voltages differentially the voltage dependance will be reduced. But the resistors will vary down the chain so the LSB at the bottom will differ from the LSB at the top. Even if you had a good model, the only way to compensate for this would be to adjust the length of the resistors down the chain, which goes against all matching rules.

I've only seen crude models for the volt-co. We used to use JFETs for a model, which didn't work all that well but at least it told you when you were doing something dumb. It is actually a hard problem to model since the volt-co is non-linear, but the value must be the same if the terminals are reversed. Using the average of the end-points voltages only works if the volt-co is linear. You can also wind up with two solutions for resistor value, one of them being negative. Talk about causing convergence problems! It took me about three months to debug that problem, and another month to convince the modelers that their model was messed up! I'm skeptical of MOS models so I'd believe resistor models even less unless something has changed in the last few years. I'd never design something that depended on them being very accurate because I've seen too many designs fail because someone put too much faith in what the simulator told them.

The design rules should have some info on volt co and max current density. In addition, some models do include the effect of self heating.

rg

---------- Post added at 19:27 ---------- Previous post was at 19:07 ----------

Jgk - if you do get a definitive answer on the self heating please let us know. I got a few hits with google scholar for polysilicon self-heating but I don't have access to the papers.

Hi all,

I have followed the spec of the N+diff resistors which can handle 800uA/um. I thus have a 3um wide resistor just for some extra protection. This resistor ladder is used to supply the Vrefp and Vrefm to a switch cap DAC and is single ended. Also I would think I should be fine since the VC is modeled with these resistors after finding it in the PDK. I have also put a 2um wide ring around the resistors just to absorb anything heat from hitting other devices. Since it really looks like the VC is modeled, I would think these N+diff resistors then are the correct choice?? Correct me here if wrong.

Also can you provide the links to the polysilicon self heating?

Jgk

As long as the models show that the error is much less (maybe a factor of two?) than you can tolerate they'd be fine. I just would NOT trust the models enough to try to tweak the size of the resistors to compensate for the temp co if it was really important. If you are going to burn up that much area you could probably use poly. Knowing how to calculate heat gradients is a useful - wish I knew how.

Try Steinmann, "Simple Analytical Model of the Thermal Resistance of Resistors in Integrated Circuits," Trans on Electron Devices, 2010.

Well I stumbled across some numbers for a 180nm process and I appear to be flat out wrong on how much this circuit will heat up. Score one for Erik, I would have had J build a flamethrower .

I won't give the exact numbers, but the equation is about 100*(I/W)^2. (where I is in mA and W is in um). This is for a resistor with sheet resistance of about 250 ohm/sq.

So, for 2 mA current in a resistor with a width of 1um the temp increase will be 100*(2/1)^2 = 400 C. Oh my, well maybe you could change your thesis to "A New Approach to One-Shot Flashbulbs."

At the maximum current density with no similar devices within 5um the temp increase is still 100C. Don't push the limits for sure.

Luckily it is inversely related to the square of the width, so a width of 5um only increase the temp by 16 C.

Remember, this was for a 180nm process so your flamage may vary. I expect temp is proportional to the square of the poly thickness so 90nm could be a lot worse.

rg