digital design using logic gates

why pmos is used as pull-up and nmos as pull-down? why not the other way round?
thanks in advance...

NMOS can pull-down output to 0V but it can pull-up maximum to VDD-Vtn. So it is bad-1 and good-0. PMOS can pull-up output to VDD but it can pull-down to Vtp. So it is bad-0 but good-1 where Vtn,Vtp are threshold voltage for NMOS and PMOS respectively.

If we swap the transistors of an inverter that means NMOS will acts as pull-up transistor and PMOS acts as pull-down. So,
1. when input is HIGH then PMOS is in cut-off region and NMOS pull-up
output to HIGH state. But output voltage will Vtn( i.e threshold
voltage for NMOS) less than VDD. NMOS is BAD-1 switch.

2. When input is LOW then NMOS is in cut-off region and PMOS pull-down
output to LOW state. But output voltage will Vtp( i.e. threshold
voltage for PMOS) high than VSS. PMOS is BAD-0 switch.

So we have less output voltage swing and less noise margins.

Nmh(Noise margin in HIGH state)= Voh-Vih
Mml(Noise margin in LOW state)= Vil-Vol

Voh= Maximum output voltage available in high state
Vih= Minimum input that can be considered as high
Vil= Maximum input voltage that can be considered as low
Vol= Minimum output voltage available in low state

too good explanation

Keep it up yadavvlsi

thanks Mr. yadav.......:-D