edabrduser
Junior Member level 2
I've an opamp where the first stage is a folded-cascode and second stage is class-A stage. It is miller compensated with the feedback path of the cap connected at the cascode of the first stage instead of the output of the first stage to avoid the RHP zero. The open loop phase margin is some 60 degrees but when connected in unity-gain buffer mode, I see gain peaking.
The load it modelled as a pi-network with 1pf cap, isolation resistor of 1k and loading cap of 20pF. What can I do to reduce the gain peaking? Cadence stb analysis with iprobe says that phase margin is 60 degrees at 45MHz and GM is 3.7dB at 100M.
If I were to add a zero to the miller-capacitor with a resistor, at which frequency should this be added? I can increase the isolation resistor as the output load is only capacitive (off-chip buffer)
The load it modelled as a pi-network with 1pf cap, isolation resistor of 1k and loading cap of 20pF. What can I do to reduce the gain peaking? Cadence stb analysis with iprobe says that phase margin is 60 degrees at 45MHz and GM is 3.7dB at 100M.
If I were to add a zero to the miller-capacitor with a resistor, at which frequency should this be added? I can increase the isolation resistor as the output load is only capacitive (off-chip buffer)
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