False path set on design

Can a path that starts at an input port of the chip and ends at the output port of the chip (I-O path) be fasle path? Please let me know on what reasoning thst I-O path be a false path.

If I understand your question correctly, you are asking if input to output path can be set as false path.

This can be or can not be set as a false path depending on the design. Generally these paths will be analysed with constraints applied at input and output pins. If you are aware that this is a non critical path and can be ignored, these paths can be set as false paths.

As jeevan.life said it may or may not be false path. It depends on your design. False path is that timing path for which STA tool is instructed to ignore its timing requirements (setup, hold). Typically false paths are present in the design because of the following reasons.
1) The path is functionally never exercised.
2) There are some unused ports of a reused IP which form these false paths.
3) Synthesis tool introduced flip-flops which break inadvertent combinational loops in the design which cause false paths.
4) Control signals that aid in the testability of the design should not be constrained during normal mode of operation, so mark them as false paths.

Suppose an I-0 path is such that its input to the chip does not come from a sequential output and the chip output of that path will not go to any sequential element. Is it a false path then? To remind one thing is that when I say I-O path I want to mean that path is a combinational path inside the chip.



Jeevanlife

What constraints are you meaning when you write that generally we constraint such an I-O path?

sun_ray said:

Suppose an I-0 path is such that its input to the chip does not come from a sequential output and the chip output of that path will not go to any sequential element. Is it a false path then? To remind one thing is that when I say I-O path I want to mean that path is a combinational path inside the chip.



Jeevanlife

What constraints are you meaning when you write that generally we constraint such an I-O path?

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As far as constraining is concerned, In case of a block in the chip, This input needs to come from another source outside the chip. You need to set the arrival and required times at the input and output pins in order to analyse the path.

Also for a path with combo logic inside, if you need to register the logic at the output , then you obviously should constrain the output.

jeevan life

Your answer does not answer the question asked very directly. Can you please answer my question that was asked. You wrote that constraining is necessary if the input to the combinational path comes from a flop sitting outside the chip and also constraining the output of the pin is necessary if the output goes to a flop. Though you are indirectly trying to answer my question, but it does not directly answer my question and I need a direct answer to the point or question. Can you please answer my question to the point.

Regards

sun_ray said:

jeevan life

Your answer does not answer the question asked very directly. Can you please answer my question that was asked. You wrote that constraining is necessary if the input to the combinational path comes from a flop sitting outside the chip and also constraining the output of the pin is necessary if the output goes to a flop. Though you are indirectly trying to answer my question, but it does not directly answer my question and I need a direct answer to the point or question. Can you please answer my question to the point.

Regards

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To Answere to the point: "If the combo path doesn't get input from a register and the output is not registered does it needs to be false path'd" again depends on the design. There is no exact Yes or No that implies to all the scenarios.

jeevanlife

Can you plese answer the following two questions?

1. How can a combinational path whose input does not come from a register outside the chip and does not go to a register outside the chip needs to be constraint?

2. On what occassion a combinational path whose input does not come from a register outside the chip and does not go to a register outside the chip, not be a false path and requires timing analysis to meet the specified timing?

Regards

sun_ray said:

jeevanlife

Can you plese answer the following two questions?

1. How can a combinational path whose input does not come from a register outside the chip and does not go to a register outside the chip needs to be constraint?

2. On what occassion a combinational path whose input does not come from a register outside the chip and does not go to a register outside the chip, not be a false path and requires timing analysis to meet the specified timing?

Regards

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1> you can use set_input_delay for input and set_output_delay for the output as per your design specifications.

2> I don't understand your Q2. If this logic is floating why do you need this logic. This logic must be talking to some other chip sitting on your board or some other part of your design, If that is the case you need to time this path. If this is not going anywhere , you may as well false path it or just remove it altogether.