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ESD issue for gate-driven power-clamp

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littlej_zju

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We use gate-driven power clamp structure for power pad ESD protection.
As below picture,
before ESD zapping, there is a small overshoot during 0.6V~1.2V;
after ESD zapping, the overshoot is higher, that's to say, there is higher leakage.

But, function test and leakage test at 3V both pass.
Can I say ESD passed?
How can I explain this IV curve?

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I'd repeat that curve-pull and see if maybe you just had some
trapped charge that swept out (the peak is peculiar in a DC
I-V, but that is an ideal that a parameter analyzer only comes
close to). See if the I-V is the same in both directions too.

Since it's gate triggered, look at whether there is a risetime
dependence. Maybe something in the gate driver circuitry
got "bent".
 
dick_freebird said:
I'd repeat that curve-pull and see if maybe you just had some
trapped charge that swept out (the peak is peculiar in a DC
I-V, but that is an ideal that a parameter analyzer only comes
close to). See if the I-V is the same in both directions too.

Since it's gate triggered, look at whether there is a risetime
dependence. Maybe something in the gate driver circuitry
got "bent".
Click to expand...

Thanks a lot. I will try IV curve in reverse direction.
As below table, leakage current is measured at different voltage level (0.5V~1.0V) in ATE. It is just leakage, not I/V curve.
Leakage shows higher for ESD-zapping. But, leakage is almost same at 3.0V.
I assume that some devices shift, but can't explain it.
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