gezzas525
Full Member level 3
My university is trying to sort out the Silicon ensemble and buildgates software packages, the requirement is to do timed simulation of a standard cell library but iam not sure how to do this. Build gates will synthesize the design from vhdl and silicon ensemble will convert the design to gds2. Now I want to do a timed analysis, originally the plan was to use modelsim with an .sdf file format however that would involve writting sdf files for the standard cell library which I have (Virtual Silicon 0.18um Library, UMC).