dear friends
plz i need a usufull and simple design to the circuit (pulse amplitude modulation) and i hope if anybody help me to simulate it in orcad
appreciate your works
thanks a lot regards
dear friends
plz i need a usufull and simple design to the circuit (pulse amplitude modulation) and i hope if anybody help me to simulate it in orcad
appreciate your works
thanks a lot regards
Last edited by keith1200rs; 01-12-11 at 09:12. Reason: remove formatting
Setup a PAM Circuit with CD4016
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http://www.doctronics.co.uk/4016.htm
"In the middle of difficulty lies opportunity." -Albert Einstein
my friend could you please give me a circuit diagram without IC's . i mean with components ( op Amp - R-L-C......)
thanks a lot
Example circuit
h**p://www.sta-tn.com/IJ_STA/Papers/IJSTA_V3N2_dec_2009/P8_IJSTA_V3N2_09.pdf
PAM with CD4016 Simulation in Proteus ..
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another Example
h**p://cc.ee.ntu.edu.tw/~wujsh/PC%20Chapter3.ppt
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More examples with JFET
h**p://ptuece.loremate.com/acs/node/9
"In the middle of difficulty lies opportunity." -Albert Einstein
please can you make the simulation with RC or JFET wit the values
can you make a simulation or just give the values for these components
regards
project.jpg
JFET Based circuits
h**p://www-personal.engin.umd.umich.edu/~fmeral/ELECTRONICS%20II/09%25c3-FET%20Project/JFET_Project.pdf
"In the middle of difficulty lies opportunity." -Albert Einstein
when i want to add pulse generator in ORCAD . there are many inputs i don't know what is the meaning of them whice are : V1-V2-TD-TR-TF_PW and PER ?
so could you please give me a random valuse to these inputs
regards
V1 Starting voltage for pulse
V2 Second voltage for pulse
TD Time delay. Voltage will remain at V1 until this specified time.
TR Rise time. Time required to reach V2 from V1 (Rise time must not equal to zero).
TF Fall time. Time required for voltage to change from V2 to V1 (Again, fall
time must not be equal to zero).
PW Pulse width. Amount of time pulse remains at V2.
PER Period of pulse. How often pulse actually repeats itself
"In the middle of difficulty lies opportunity." -Albert Einstein
sampling .jpg
could u plz give me the vaules of this design cuz my advisor want the PAM design by using sample ana hold ( and this design )
waiting ur response
regards
nothing works with me
plz another examples and easy to build it !!!
---------- Post added at 03:54 ---------- Previous post was at 03:28 ----------
nothing works with me
plz another examples and easy to build it !!!