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What does the synthesizer do for a multicycle path

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rogeret

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Hi everyone,

Somebody tells me if I have a big combinational logic in my design which will never run at the required frequency ,I can ease off the single-cycle requirement: allow more clock cycles using set_multicycle_path command. And DC will allow more clock cycles for path delay when checking for setup/hold violations.

But what will the the synthesizer do to the multicycle path.
And does the "the multicycle path" mean , in my logical design, the data of the flip-flop in the multicycle path should be sampled every 2 clocks?
 

Synthesizer will optimize logic in the same way as for singlecycle path, the only difference is that it will try to meet timing constraints for smaller frequency.

Yes, you are rightm it should be sampled every 2 clocks (or every 3 or ... it depends on how many multicycles you have defined).
 
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