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During Static timing Analysis (STA), design functionality is "NOT" checked, only timing is checked to see if it meets the timing specification. That is why gate level simulation is done with timing to see if functionality is correct with timing.
It is also true that STA does not check asynchronous interface. So simulation is necessary.
hi Sun_ray,
although STA can check timing and formal tools can check functionality between RTL and netlist, but we still need gate level simulation to run real test case with SDF! because the constrain for STA is written by people , it will have error!
The constrain is determined according to the requirement of design. So, it should be decided by people...
For digital circuits, the timing must meet the corresponding requirement otherwise the results from the circuit will be erroneous.
sdf can be used to check the functionality of the circuits.
For many digital designers, if the digital circuits are not so big or/and don't have interface with other big circuits, they just roughly estimate the sdc. Timing analysis accuracy seems not so important for them.
In STA we don't check functionality of the circuit. We analyse only the timing . Functionality is checked in case of DTA. So to verify the functionality we need the simulation.
DTA is Dynamic Timing Analysis, Here we make use of all the vectors and time the design. STA came up because DTA is very time and memory consuming. Gate level simulations are used also for checking the violations(constraint related) after the final routing and timing cleanup using STA tool. Since constraints are written by designers, and STA takes these constraints for the analysis there can be a possibility that some paths may be wrongly analysed . So to verify this we use gate level simulation.
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