Off-chip decoupling of a ring oscillator

I have a on-chip ring oscillator running at 500MHz.
Depending on the tuning voltage, it may run as low as 250MHz.

The vdd, gnd supply of the rin oscillator is not connected to anything else on-chip
Unfortunately, I put in, little, or non existant on-chip decoupling cap.
Therefore, decoupling will have to take place offchip after 2nH of bond wire.
Will 100pF in parallel with 10pF be enough?
It would be great if capacitor arrays are available(multiple 100pF in parallel with multiple 10pF), but I don't have them
I'm assuming 100pF in parallel with 10pF in parallel with 10nF to be safe...
Does this sound reasonable?

I also have a question on the difference in the order of magnitude between the parallel caps.
Somtimes people use 1uF in parallel with 100uF. order of magnitude x100
Somtimes people use 1uF in parallel with 10uF. order of magnitude x10
which one is better in terms of lower antiresonant effect???
It seems that people have different opinions on this... Hmm.

A power supply decoupling cap first and foremost should have a low impedance for the frequency which it should short-circuit. Hence electrolytic capacitors (ELCOs) in the 100µF range are good against 100/120 Hz line frequency interferences, but not so good against interferences in the middle and high (RF) frequency ranges because of their (relatively) high series-L and -R (ESR) impedances. For the decoupling of such frequencies, mostly ceramic caps are used (in parallel to a possible ELCO).

It depends on the frequency, which values will be chosen: To decouple audio amplifiers with frequencies in the 10kHz range, a few additional 10µF ELCOs on board could be perfect, for converters in the 100kHz range, some 1µF ceramic caps would probably fit better, against 1..10MHz distortion ≈100nF cercaps would be fine, and for decoupling several 100MHz interferences probably 1..10nF cercaps would do easily -- and perhaps even better than larger ones.

Without on-chip decoupling the performance will be pretty
dismal, edge rates are going to be weak.

In the past I've found a useful crutch to be, placing a chip
capacitor in the package cavity "tombstoned" near the VDD
pin(s) and skip-bonding the VDD wires from post to cap to
pad, with VSS down-bonded to the cavity and up-bonded
to post. At least you can minimize the AC current loop
indictance like that. Of course I work almost entirely in
hermetic packaging and have Nice Lab Ladies to do my
wirebonding on demand.

dick_freebird. Can you elaborate?
I'm doing the bonding for my COB and like to know your technique.
I'm kinda confused

There is a die attach paddle (ground plane), yes? With enough
extent that a (say) 0402 chip cap could be stood on end and
soldered to the "ground plane"?