rocky.king07
Newbie level 6
I am trying to simulate a 14 bit pipelined ADC with eldo and HSPICE simulator for INL, DNL and missing code. With these simulator I am getting simulation time more than 100 Days. How can I reduce runtime. In simulation I have applied ramp input which slope is adjusted such that its increasing 0.25 LSB per clock. Is it right way to simulate ADC for INL DNL. What is normal practice to simulate 14 Bit ADC.