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How to simulate INL, DNL and missing code of ADC?

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rocky.king07

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I am trying to simulate a 14 bit pipelined ADC with eldo and HSPICE simulator for INL, DNL and missing code. With these simulator I am getting simulation time more than 100 Days. How can I reduce runtime. In simulation I have applied ramp input which slope is adjusted such that its increasing 0.25 LSB per clock. Is it right way to simulate ADC for INL DNL. What is normal practice to simulate 14 Bit ADC.
 

Most of the causes from INL.DNL are from device mismatch. So you've gotta multiply your simulation time by a few hundred fold.
That is why most ADC design is done in MATLAB or other faster platforms. Just so that it could be simulated at a much shorter timeframe.
Or alternatively, if you know where your worst case INL/DNL is going to be, just simulate in that region of codes.
 

i am unable to understand how ADC design can be done in matlab ? matlab is just a behavior level simulator. How one can correlate matlab results with actual design? suppose we are getting no missing code in matlab simulations, but my question is is it necessary to measure inl/dnl for each code to see the performance of ADC, what is general industry practice?
 

You can try to use behavioral models for the logic part of your ADC. In Eldo there are behavioral gates. This reduce the simulation time compared to transistor level gates.
 

But actual circuit may different from behavioral model. So actual circuit simulation result may different from behavioral model and fabricated chip may or may not work.
 

I would discourage you from trying to simulate DNL/INL at transistor level. For 10-bit ADC and an accuracy of 95%, you would need about 620000 samples (not reasonable to simulate). The explanation for this can be found at **broken link removed** website.
Behavioral modelling is used instead, as suggested in the above posts. In order to do that, you need to fully understand the sources of static mismatch in your design (DNL/INL are static parameters).
 

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