VHDL Processes (Adding Delays)

I am trying to design a tic tac toe game for a project. I need to detect the players first move and then wait 2 seconds before the machine makes a move. I wanted to make the move by the machine in the same "process statement" after the player makes his move but I can't add in a delay inside the process.

Should I use a counter and enable this counter everytime the player makes a move? After the player makes him move I could set a signal high and then use this signal in the counter process in the sensitivity list to activate the counter. How should I create this 2 second delay outside of the process? Any other ideas?

Thanks a lot for your help!

A counter is going to be the easiest way. It's not the best method, however for you application, it will most likely work just fine - as long as you don't run out of space on the chip. Depending on your input clock, having a two second delay may require a rather large counter, however you should get the desired effect.

Thanks for your reply BlackHelicopter. I was planning on writing up the code as shown below. I am going to use signal user_press to signify when Key1 is pressed. When signal user_press = '1' then the counter begins and the counter will signify when the counter has waited for 2 seconds by the signal cntr_done. Both of these process are only sensitive to the clock (clk). My counter assumes 1KHz (for simulation sake) so the counter would have to run through 2000 cycles to wait 2 seconds. Does this look correct or are there issues with this implementation?

Thanks,

Dan

-----------------------------------------------------

architecture behav of example is
signal cntr_done : bit;
signal user_press : bit;
begin

COUNTER_PROC: process(clk)
variable cntr : integer;
begin
if rising_edge(clk) then
cntr_done <= '0';
if reset = '1' or user_press = '1' then
cntr := 0;
elsif cntr = 2000 then
cntr_done <= '1';
else
cntr := cntr + 1;
end if;
end if;
end process;


SOME_PROC: process(clk)
begin
if rising_edge(clk) then
if Key1 = '1' then
user_press <= '1';
else
user_press <= '0';
end if;
end if;
end process;
end if;
end if;
end process;

----------------------------------------------

Try something more like this..

Counter:

Your second process needs a little work, there are: two too many "end if;" statements and one too many "end process" statements, it will not compile.


Take a look at this for a simulation, it's very similiar:
VHDL for FPGA Design/4-Bit BCD Counter with Clock Enable - Wikibooks, open books for an open world

See if this makes any sense to you.

Also one thing that might help "visualize" what you are doing, is after you have compiled, open "RTL Viewer" in whatever tool you are using, and observe the logic that is getting generated from your code. Your code code is actually getting turned into "this logic" on the FPGA.

Thanks BlackHelicopter...that information was definitely helpful!