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Issue with timing delay characterization - convergence with hspice

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satishgra

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Hi,

While characterizing one of my IO buffer for a particular timing arc for various values of load capacitance, I see that the simulations are converging when the load is cap values are higher. Unfortunately, they are not converging when the load cap value is set to a lower value. I find this rather strange :)

As per my understanding, wen the load cap is less, it should easily converge. Am I wrong with my statement.

Exact numbers :
slew is constant
load cap : 100fF { converges }
load cap : 1fF { runs into convergence issues }

Quick help is solicited.

Regards,
Satish
 

Well, for starters 1fF cannot be had. But it probably shows
that something in the MOS models is not proper (like the
parasitic capacitances are absent or absurdly small).

You might need to increase the accuracy and/or decrease
the timestep.
 

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