altera cyclone IV pin assignment problem

hi guys,
I assign pin assignment for Altera FPGA Cyclone IV then this Error Message occur:


Error: Cannot place pin ovMemBa[0] to location B3
Error: Can't place VREF pin B5 (VREFGROUP_B8_N1) for pin ovMemBa[0] of type output with SSTL-18 Class I I/O standard at location B3
Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 8 when the VREF pin B5 (VREFGROUP_B8_N1) is used on device EP4CE55F23C7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info: Location A4 (pad PAD_372): Pin ovMemAddr[12] of type output uses SSTL-18 Class I I/O standard
Info: Location B4 (pad PAD_373): Pin ovMemAddr[3] of type output uses SSTL-18 Class I I/O standard
Info: Location F8 (pad PAD_374): Pin oMemCke of type output uses SSTL-18 Class I I/O standard
Info: Location G8 (pad PAD_375): Pin onMemCs of type output uses SSTL-18 Class I I/O standard
Info: Location A3 (pad PAD_378): Pin ovMemAddr[10] of type output uses SSTL-18 Class I I/O standard
Info: Location D6 (pad PAD_380): Pin ovMemAddr[13] of type output uses SSTL-18 Class I I/O standard
Info: Location E7 (pad PAD_381): Pin ovMemAddr[4] of type output uses SSTL-18 Class I I/O standard
Info: Location C3 (pad PAD_382): Pin ovMemAddr[6] of type output uses SSTL-18 Class I I/O standard
Info: Location C4 (pad PAD_383): Pin ovMemAddr[7] of type output uses SSTL-18 Class I I/O standard
Info: Following 12 location(s) shared the same VCCIO and ground pair, and 9 pin(s) are placed
Info: Location A4 (pad PAD_372): Pin ovMemAddr[12] of type output uses SSTL-18 Class I I/O standard
Info: Location B4 (pad PAD_373): Pin ovMemAddr[3] of type output uses SSTL-18 Class I I/O standard
Info: Location F8 (pad PAD_374): Pin oMemCke of type output uses SSTL-18 Class I I/O standard
Info: Location G8 (pad PAD_375): Pin onMemCs of type output uses SSTL-18 Class I I/O standard
Info: Location (pad PAD_376): unused
Info: Location (pad PAD_377): unused
Info: Location A3 (pad PAD_378): Pin ovMemAddr[10] of type output uses SSTL-18 Class I I/O standard
Info: Location B3 (pad PAD_379): unused (but has pin assignment of ovMemBa[0])
Info: Location D6 (pad PAD_380): Pin ovMemAddr[13] of type output uses SSTL-18 Class I I/O standard
Info: Location E7 (pad PAD_381): Pin ovMemAddr[4] of type output uses SSTL-18 Class I I/O standard
Info: Location C3 (pad PAD_382): Pin ovMemAddr[6] of type output uses SSTL-18 Class I I/O standard
Info: Location C4 (pad PAD_383): Pin ovMemAddr[7] of type output uses SSTL-18 Class I I/O standard



all problem posted in the internet(with same error message) is because of bidirectional signal but in my problem all locations are assigned as output. do anyone has any idea how to solve this problem?

1. move some pins to other vccio group if possible;
2. if not - change 'device and pin option' -> 'pin placement' -> max. output
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J.A

At first sight, you didn't observe the pin placement rules. Sometimes, similar conflicts are brought up if you forget to define necessary output enable groups for bidirectional signals. But the address pins are driving out permanently, they simply don't tolerate voltage referenced input pins beneath them.

P.S.: Where do you see this option?

change 'device and pin option' -> 'pin placement' -> max. output

Click to expand...

FvM, i got what u mean and yes i think i dont define necessary output enable group for the signals. so i output enable group all ddr2 signals and the problem solve.
j_andr, i cant find the device and pin option -> pin placement -> max. output

zel said:

j_andr, i cant find the device and pin option -> pin placement -> max. output

Click to expand...

assignments -> device -> device and pin options <right upper corner> -> pin placement


if you have a board ready and can't change pin assign. it may help, under some conditions;
better approach is to let the software to assign the pins [with some guideline of course]
and then design the board;
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it has to be noted this should be 'last chance' solution rather then a practice
as you exceed safe work limits set by altera;

J.A

That's how I see the pin placement tab for Cyclone IV E in Quartus V11.0 Web Version. Which Quartus Version + Chip you are talking about?

FvM said:

That's how I see the pin placement tab for Cyclone IV E in Quartus V11.0 Web Version.
Which Quartus Version + Chip you are talking about?

Click to expand...

any quartus/device;
problem is in 'auto device selected';



if you select any device you should see such picture:



then you can select 'override electromigration ...' option and change the default settings;
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J.A

Thank you, I should have read the auto device hint. The problem in the original post is however not related to maximum output current according to electromigration rules.

FvM said:

The problem in the original post is however not related to maximum
output current according to electromigration rules.

Click to expand...

may be;
the statement from the original post:

Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 8 when the VREF pin B5

Click to expand...

suggests it can be the a problem with a number of outputs in one vccio group;
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J.A