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how to convert a xilinx system generator model to a bit file?

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shumail

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hi all,
can anyone help me converting a xilinx system generator block model to a bit file for loading in an fpga?
 

There's a number of flows for this. The easiest is to just tell SysGen to generate the bitstream and use iMPACT. This is simply a configuration option in the System Generator token. Also, you can generate hdl or an .ngc and you can continue through the rest of the ISE flow (or planahead flow if you're in 13.3). I suggest you read the sysgen getting started guide and the sysgen users guide
 

thank you so much...
 

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