Ram RTL in VERILOG HDL

dll_fpga said:

RAMmodule ram (addr, clk, din, dout, we);
input [1 : 0] addr, din;
input clk, we;
output [1 : 0] dout;
reg[1:0] memory[3:0];
reg[1:0] dout_r;
always @(posedgeclk) begin
if (we)
memory[addr] <= din;
dout_r <= memory[addr];
endendmodule

I think the above code is a behavioral code of a ram.
How can we write a RTL code of a ram with an array of registers and a seperate address decoder .
How will the memory designers write the RTL of memories?or they write the behavioural model?

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pini_1 said:

You may be interested in looking at this site:
"...memory HDL models

This page has links to some memory VHDL models, which I used for simulations.

An asynchronous, written in VHDL, sparse memory model to reduce memory consumption: async vhdl memory
A synchronous write sparse memory model. The read is asynchronous. This model is very poplar with most FPGA devices. sync vhdl memory
A synchronous write sparse memory model, written in VPI - C-Programming interface to the Verilog HDL. sync VPI memory ..."
**broken link removed**

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dll_fpga said:

does anyone know any links for syncronous sram memory model provided by any major memory manufacturer.Any links or documents...please

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