Realization of dual_clock with fixed phase shift in Low Frequency Mode?

Hi,
I need to generate a couple of clocks which has fixed and adjustable phaseshift. One frequency is 2 times of the other one. e.g. in my case, one frequency is 3Mhz, one is 6Mhz. I use DCM due to it's merit of high phase shift resolution.

Becasue my design work in LFM (low frequency mode), I cannot directly generate the two clocks from CLKIN and CLKDV(or CLKFX). becasue in LFM, if using CLKIN in LF, only CLKFX can be used. however CLKFX cannot be lower than 32Mhz. So I used a FSM to generate the other LF clock by frequency-dividing the output of DCM.

I am planning to do it like this:



Here, if i use the 6Mhz signal as the feedback to CLKFB, can the 6Mhz clocks be aligned with the 3MHz clock? I mean, whether the phaseshift of 3Mhz and 6Mhz signal be fixed ?

Sorry, forgot to say, my target device is Xilinx Virtex5.

Thanks very much!

Hi chifalcon,

I dont know the limitation of Xilinx Virtex5's DCM. My suggestion is that why cant you do like this....

View attachment untitled.bmp....

if its a blender please leave it....

Hello, imbichie,
Thanks for your reply.

I am a rookie in DCM. So please correct my design.
Here, in Xilinx DCM, a phase shift resolution 256 of the CLKIN's clock period can be achieved. in my design, the higher phaseshift resolution the better. If I use a f/2 directly from 6MHz to get the 3MHz as you suggested, it seems that I cannot take advantage of the merit of high phaseshift resolution in DCM. Right?

Can you please give a guidance? Thanks!

imbichie said:

Hi chifalcon,

I dont know the limitation of Xilinx Virtex5's DCM. My suggestion is that why cant you do like this....

View attachment 64212....

if its a blender please leave it....

Click to expand...