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finding Ft in cadence

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the_falcon

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Hi all,
I am trying to find Ft in cadence for just a single PMOS transistor and I am not able to do it so far. I am using a single PMOS, a DC voltage source Vdc , one in drain and one in gate for biasing and also an DC current source idc acm parameter as 1 A . this current source is in series with my DC voltage source for gate.

I ran an ac analysis and tried to find the current ratio between drain and gate through calculator. then i tried to plot it against frequency. I am sure that the graph is wrong.

so could anyone tell me as how to plot this one in a right way.many thanks in advance.

falcon
 

I ran an ac analysis and tried to find the current ratio between drain and gate

The current ration between drain and gate?
Do you know that the gate current is a parasitic parameter that has nothing to do with gain properties of the device?
 
first thanks for your reply
yeah I know it already and I also went through another post where you described it with full detail
but thought of trying to process it as per its regular definition for a try
so if you can help me, could u tell me the actual way to find the Ft in cadence for a single PMOS transistor
thanks
 

What is the definition of ft for a PMOS? You only can measure/simulate a parameter if you know its definition.
 

Fine.
It can be defined as the frequency when the ac short circuited current gain factor goes to unity.
It defines the speed of the transistor and its factual usually to choose the maximum operating frequency somewhere below this Ft frequency.
and it usually depends on the overdrive voltage before velocity saturation but not once the velocity saturation is reached
It also depends inversely proportional to the square root of length before velocity saturation but on just the length after the velocity saturation

I just wanted to see it happening in cadence but I am not able to make it.
So would be be kind enough to show/tell me some suggestions about how to go about and compute it in Cadence
Thanks


Falcon
 

Hi Falcon,

to simulate a specified device parameter I think it is logical simply to follow the specification.
That means: Fix the dc bias point, inject an ac voltage and watch the ac output current - until it approaches zero at a certain frequency called Ft.
(ensure ac short circuit at drain node).
 

Thanks LvW
I will try it out and let u know about it once I am back to school after the weekend
Cheers
 

I ran an ac analysis and tried to find the current ratio between drain and gate

The current ration between drain and gate?
Do you know that the gate current is a parasitic parameter that has nothing to do with gain properties of the device?
I was under the impression that the transition frequency is the frequency in which current gain is 1.
For MOS, it means that the current that couples across and/or used to charge the Cgd/Cgs equals the drain current.
 

Hi Checkmate, you are right.
I have mixed 0 dB with absolute zero.

Hi Falcon,

look at this link - it gives you all information needed.
Simulating MOS Transistor ft - RF Design - Cadence Community

---------- Post added at 16:00 ---------- Previous post was at 15:34 ----------

Recommendation: Read the last comment in the linked discussion (May 29, 2011)
 
---------- Post added at 16:00 ---------- Previous post was at 15:34 ----------

[/COLOR]Recommendation: Read the last comment in the linked discussion (May 29, 2011)

Everyone is entitled to his opinion, but I disagree with the poster.
The gate leakage and parasitic capacitances is precisely the main reason for bandwidth limits for MOS.
Berkeley notes show the same thing.
https://inst.eecs.berkeley.edu/~ee105/fa98/lectures_fall_98/111698_lecture28.pdf
In principle, the transition frequency seeks to characterize the bandwith of a real device, and that has to take into account all parasitics/leakages which comes with it. Only then can you truly characterize a process.
 
Thanks a lot for both the weblinks you people suggested me to go through
it was helpful
thanks again

falcon
 

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