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Multi-Level Clock Gating

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kumar_eee

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What is meant by Multi-Level Clock Gating? How does it differs from normal clock gating?
 

by design you could define a "master" clock gating, and add local clock gsating (in RTL or by synthesis tool) to reduce the power consumption.

The idea is to place the clock gate as closest as possible of the clock source, to have the maximum of buffers after this clock gate to reduce the clock tree consumption. Then one master clock gate close to the clock source and many local clock gate to inactivate the flop (for example).
 
It is a hierarchical clock gating. Gating cell exist in the root, the branches and the leafs of the CT.
 
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