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Mixing of Blocking and Non blocking assignments.

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optimuz

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Hi,
I am having a problem when I am mixing Blocking and Non Blocking assignments .
In the below code the tool is not giving any errors.
always @ (*)
begin
x=1;
z<=0;
end

But for this one , tool is giving error saying "cant mix blocking and non blocking"
always @ (*)
begin
x=1;
x<=0;
end

Can any one explain me that can be the probable reason why for a same variable mixing is not possible and for different variable mixing is possible.

Thanks
 
Last edited:

You are trying to assign two different constants to a same variable at the same instance of time.
 

But my question is why tool is not taking a precidence like what it does for two variables. Anyway as its non blocking and blocking , it wont be assigning at the same time.
 

optimuz said:
But my question is why tool is not taking a precidence like what it does for two variables. Anyway as its non blocking and blocking , it wont be assigning at the same time.
Click to expand...

in verilog all the statements are executed at same time, that's the main special feature of that..here in your example you are using blocking and non blocking statements..
actually verilog code is executed in four quarter cycles
1. all the blocking and non-blocking statements of rhs are evaluated and blocking statements are updated to lhs
2. all the system tasks are executed
3. all the non-blocking statements are updated to lhs
4. PLL's are executed
so, in first sim cycle X=1 wil be displayed and if you look in second sim cycle then you can observe that X=0..you run the program on CLK then definitely you'll get that..
 

You could possibly design a construct, where mixing bl. and nbl. assignments for the same variable won't cause logical inconsistencies. In this case, simply refer to the fact, that it's explicitely prohibited by the Verilog standard.
 
@sharif.shiek
Thanks for ur detail reply. For simulation purpose it is working fine. I have done with Xilinx ISE. But Synplify Pro which I am using for synthesizing is giving me error.
My doubt is why it is giving error for ONLY second code , even though I am assigning constants .
 

My previous statement about allowance of mixing bl. and nbl. statements in fact doesn't apply to simulation. It's not forbidden by the Verilog standard itself. But it's e.g. said in synthesizable Verilog specification IEEE Std 1364.1.

A variable assigned in an always statement shall not be assigned using both a blocking assignment (=) and a nonblocking assignment (<=) in the same always statement.
Click to expand...

Also before IEEE Std 1364.1, it has been well known, that these mixed statements aren't synthesizable. A detailed discussion can be found in the classical Cummings paper, see: https://www.edaboard.com/threads/175727/#post737345
 

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