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current mirror: presim versus post-sim

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allennlowaton

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Hello EDA fellows,

I've been doing the presim and the postsim of my Iref and Ibias circuit lately.(figure shown below)
The problem now is the performance of the post-sim is unacceptable.
From the figure below, it can be seen that the voltage at N3 during the post-sim is almost twice as that
of the presim. I don't know if there's something wrong in my layout, though LVS had been passed.
Currently, the matching ratio of MP4 and MP5 is 1:20, I planned to reduce it to 1:2 which means I will increase the IREF value in order to obtain the same IBIAS value. Can you suggest an optimized matching ratio for this?





 

allennlowaton said:
the performance of the post-sim is unacceptable.
Click to expand...
From your 2nd image it seems both the pre- and the post-sim results aren't stable.

allennlowaton said:
Currently, the matching ratio of MP4 and MP5 is 1:20
Click to expand...
Did you use 1:20 fingers/transistors? Symmetrical layout?
If so -- and the current ratio is still wrong -- I'd suggest a 2-stage ratio 1:4 and 1:5 . Always same finger lengths!
 
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    allennlowaton

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I did a post-simulation with my OP alone. I found out that there's a 20mV~30mV DC difference on its inputs. The gain is not anymore positive. Further simulation shows that the said OP can only afford to have 2mV DC difference on its inputs. How can I improved my OP to obtain such requirement?
 

I'm sorry. i don't know your structure so i can't give you some useful advice. Maybe your layout have some problem.
you can upload the curve of the simulation about the OP both the pre and post.
Did you notice any difference of the VB2 between pre-simulation and post-simulation?
 
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