Srini6079
Newbie level 1
Hi ,
I have written and executed my verilog code for 16-bit kogge stone adder on quartus. The netlist format obtained was in edif format. I use Atlanta and hope for test pattern generation and fault simulation. Unfortunately the input netlist format for atalanta is ISCAS89 netlist format. Can someone help me to generate a ISCAS89 netlist format from verilog code or suggest any tool to do that. If someone already has the ISCAS89 format netlists for 8-bit/16-bit/32-bit/64-bit kogge-stone adder. can you please email it to me
Thanks in advance,
Srini
I have written and executed my verilog code for 16-bit kogge stone adder on quartus. The netlist format obtained was in edif format. I use Atlanta and hope for test pattern generation and fault simulation. Unfortunately the input netlist format for atalanta is ISCAS89 netlist format. Can someone help me to generate a ISCAS89 netlist format from verilog code or suggest any tool to do that. If someone already has the ISCAS89 format netlists for 8-bit/16-bit/32-bit/64-bit kogge-stone adder. can you please email it to me
Thanks in advance,
Srini
