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how to add a buffer to seperate the port from inner logic?

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kermit

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If we just want input port only connecting with one cell in the design,then this cell maybe drives a lot of cells.How to add constrain when synthesissing in PKS?
 

Re: how to add a buffer to seperate the port from inner logi

kermit said:
If we just want input port only connecting with one cell in the design,then this cell maybe drives a lot of cells.How to add constrain when synthesissing in PKS?

I think you can find the command about setting the fanout. I use those knid of command in DC or BG, not in PKS, so it need to search in GU.
or you can point the cell X8 or X16 and more.

Good Luck
 

Re: how to add a buffer to seperate the port from inner logi

Well, when you find setting fanout backfires on your synthesis, you may try instantiate a buffer instead.
I was aware that setting fanout might cause other part of the design to go nasty and in order to prevent this havoc you need to write more compilcated synthesis scripts. :roll:
 

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