pichuang
Newbie level 6
Hi everyone,
Has anyone had experience with post layout mismatch monte-carlo simulations with TSMC kit? I am using the 65nm process and is unable to perform the post layout mismatch simulation. I am able to do the mismatch simulation in schematic. However, when I tried to extract the parasitic capacitance using Calibre PEX, I have the following problem:
If I select "Use Names from" to be source based, Calibre doesn't seem to recognize the transistors as mac devices (appropriate layer has been added)
If I select "User Names from" to be layout, Calibre does see to recognize the transistors as mac devices. However, it seems to double/triple count the device.
Has anyone else encountered this problem before? Any suggestion/help is really appreciated.
Pierce
Has anyone had experience with post layout mismatch monte-carlo simulations with TSMC kit? I am using the 65nm process and is unable to perform the post layout mismatch simulation. I am able to do the mismatch simulation in schematic. However, when I tried to extract the parasitic capacitance using Calibre PEX, I have the following problem:
If I select "Use Names from" to be source based, Calibre doesn't seem to recognize the transistors as mac devices (appropriate layer has been added)
If I select "User Names from" to be layout, Calibre does see to recognize the transistors as mac devices. However, it seems to double/triple count the device.
Has anyone else encountered this problem before? Any suggestion/help is really appreciated.
Pierce
