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negative delay annotation at ncelab

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Dvir

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Hi

We are at the process of simulating a gate level post-route verilog netlist using ncsim. We see a few INTERCONNECT information in the sdf file that shows negative delay.
While elaborating we get the following warning code (SDFNDP):
An attempt was made to annotate a negative delay value or pulse limit to a specify path or interconnect delay. The value will be set to zero.

We are aware that vcs has a switch -negdelay which annotates the negative delays of sdf file.

Does anyone know what is the switch for ncelab ?
 

Negative timing checks and negative delay annotations are different things.
Synopsys VCS has two switches (-neg_tchck VS. -negdelay) for negative timing checks vs. negative delay annotations.
 
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