Synthesize problems Xilinx

Hi everyone,
I am a beginner in the hardware programming and I wrote an application for fpga where the simulation run perfectly but when I try to implement it I get first a warning in the Synthesize process "More than 100% of Device resources are used" and then the map process fail with this error "The design is too large for the given device and package.".

I attached the two reports.
View attachment map.txt
View attachment Synthesize.txt
I want to use the Spartan 3E.

I have no idea from where I can start to solve this problem.
How can I reduce the number for slices that are used?
What is the unrelated logic?
Thanks for help.

Since XST issues this Warning

WARNING:Xst:1336 - (*) More than 100% of Device resources are used

and

"ERRORack:18 - The design is too large for the given device and package.



We can infer that Design requires more resources .

Number of Slices: 8814 out of 8672 101%

So I would Recommend a Change in Design

Here are some Interesting Discussions

h**p://forums.xilinx.com/t5/Archived-ISE-issues/Discrepancies-in-Slice-Utilization/m-p/7173#M1592

h**p://www.xilinx.com/support/answers/17042.htm

---------- Post added at 17:15 ---------- Previous post was at 16:58 ----------

Another important thing

Xilinx ISE features some optimization options.

Design and Optimization White paper
h**p://www.xilinx.com/support/documentation/white_papers/wp231.pdf




WP275 - Get your Priorities Right – Make your Design Up to 50% Smaller

h**p://www.xilinx.com/support/documentation/white_papers/wp275.pdf

And Follow the Recommended XST Coding style often it will produce better results

h**p://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/xst.pdf

---------- Post added at 17:21 ---------- Previous post was at 17:15 ----------

Advanced FPGA Design: Architecture, Implementation, and Optimization
Steve Kilts

there are 2 answers:
1. change your design
2. get a bigger chip.

monty81 said:

What is the unrelated logic?

Click to expand...

How about google the term: xilinx 'unrelated logic' ? I just tried, and that gave relevant results.

That advice goes for a lot of error messages / warnings. Just cut and paste into google, and quite often you get useful info.

There's a singular problem in synthesis report, that - if solved - would allow synthesis of your design in the present device:

HDL ADVISOR - 5120 flip-flops were inferred for signal <ram_array>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.

Click to expand...